Unit 6: Synchronous & Asynchronous Sequential Logic

Digital Electronics: Sequential Logic Complete Guide

Chapter 1: Flip-Flops

1.1 Types of Flip-Flops

Type	Characteristic Table	Equation
SR Flip-Flop	S | R | Q(t+1) 0 | 0 | Q(t) 0 | 1 | 0 1 | 0 | 1 1 | 1 | X	Q(t+1) = S + R'Q(t)

1.2 Triggering Mechanisms

[Clock Signal Diagram - Positive Edge Triggering]

• Level Triggered: Active during entire clock pulse
• Edge Triggered: Active only during clock transition

Chapter 2: Sequential Circuit Analysis

2.1 State Transition Diagrams

[State Diagram Example: 3-bit Counter]

2.2 Mealy vs Moore Machines

Aspect	Mealy Machine	Moore Machine
Output Dependency	Inputs + State	State Only

Chapter 3: Sequential Circuit Design

3.1 State Reduction Techniques

State Reduction Algorithm: 1. Create implication table 2. Mark non-equivalent pairs 3. Merge equivalent states

3.2 Excitation Tables

FF Type	Excitation Table
JK Flip-Flop	Q(t) | Q(t+1) | J | K 0 | 0 | 0 | X 0 | 1 | 1 | X 1 | 0 | X | 1 1 | 1 | X | 0

Chapter 4: Asynchronous Sequential Logic

4.1 Fundamental Mode Operation

• Single input change at a time
• Stable state requirements

4.2 Hazards and Race Conditions

Critical Race: Leads to unpredictable final state
Non-Critical Race: Ends in predictable state

Practice Exercises

Problem 1:

Design a sequence detector for pattern 1101 using D flip-flops

Hint: Use state diagram with minimum states

Appendix: Quick Reference

Term	Definition
Setup Time	Minimum time before clock edge
Hold Time	Minimum time after clock edge
Metastability	Unstable state violation